A network processor generally controls the flow of data between a physical transmission medium, such as a physical layer portion of a network, and a switch fabric in a router or other type of switch.
An important function of a network processor involves the scheduling of cells, packets or other data blocks for transmission to the switch fabric from the physical transmission medium of the network and vice versa. A network processor typically includes a scheduler for implementing this function. It is often desirable for a given network processor to support a number of different processing configurations, each of which may require a distinct scheduling algorithm. For example, a network processor may need to support constant bit rate, variable bit rate and weighted fair queuing scheduling algorithms. In typical conventional practice, the network processor may be configured to include separate hardware architectures to support each of the desired scheduling algorithms. However, each of the separate architectures generally requires a particular set of dedicated hardware resources, which can result in wasted resources if some of the supported scheduling algorithms are not used in a given network processor application. Also, such dedicated hardware architectures fail to provide adequate flexibility to implement different scheduling algorithms that were not specified at the time the hardware was defined.
The techniques disclosed in the above-cited U.S. patent applications address the problems associated with use of separate hardware architectures for each of a number of scheduling algorithms in a network processor. Notwithstanding the considerable advances provided by these techniques, a need remains for further improvements in scheduling algorithm implementation in a network processor.